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Open research assistant positions for the summer 2023

…ASIC chips, the ASIC physical design is one of the key skills needed. Physical design tasks include netlist synthesis, Design-For-Test (DFT), Static Timing Analysis (STA), Formal Verification (FV), Placement, Routing… […]

Open research assistant positions for the summer 2024

…will be specified based on the skills level. Good programming and digital design skills are required. Position 5: GPGPU Hardware Platform Development Modern scientific modeling and simulation problems and especially… […]

Open research assistant positions for the summer 2022

…for testing. The goal with these is to create FPGA designs for sample testing which act as an intermediate for data between the SoC sample and external data inputs/outputs. We… […]

What is FPGA prototyping?

…design but can also be run and tested on the platform with ease.” Tom works as SoC Hub researcher at Tampere University. A key aspect of the prototyping is that… […]

How to become a verification engineer?

…principle is to separate the tests from the testbench structure (environment) so that different testcases with different input stimuli can be run without modifying the environment. Small subsystem-level environments can… […]

Highlights of the SoC Hub launch

…overview of the drivers to SoC development which are 5G and artificial intelligence. 5G deployment is progressing fast, and using the latest silicon is crucial for success. Even if the… […]

Open positions at Tampere University: Postdoctoral research fellow, summer interns

…planning, testbench development, testcase development and automation for modern SoC devices. Needed competences are interest in modern SoC hardware development in form of verification and basic skills on RTL verification…. […]

Webinar: Introduction to Cadence Design Systems digital backend flow

…the webinar platform preparations we cannot accept registrations after the deadline. The webinar will be hosted at Zoom together with cloud-based design environment provided by Europractice through which attendees will… […]

Finnish system-on-chip design gets stronger as Tampere’s SoC Hub co-creators prepare to unveil a new system-on-chip tapeout

…launched last year and is coordinated by Tampere University and Nokia. The project has worked hard to develop collaboration between the University and businesses while investing heavily in system-on-chip skills… […]

Workshop: Accelerating Imaging Algorithms with Catapult High-Level Synthesis

…optimized memory architecture (60 minutes) Wrap-up (15 minutes) Your Instructors Mike Fingeroff HLS Technologist for the Catapult HLS Platform at Siemens EDA (formally Mentor Graphics) since 2002. His areas… […]