Open research assistant positions for the summer 2024

Join our growing team at Tampere University! We are now looking for several research assistants to work with us during the summer 2024.

The SoC Hub team handles all aspects of System-on-Chip design: specification, automation tools, RTL design, verification, SW architecture and tools, physical design and sample testing of chips fabricated in leading foundries. This includes handling of system topics like memory architectures, system throughput, use case base verification as well as dedicated module developments such as ML/AI, security, interconnect, RISC-V architectures as examples.

We are looking for enthusiastic, hard-working and motivated Research Assistants with BSc degree to work for SoC Hub. The interns will be supervised by our researchers and staff.

Job descriptions

Position 1: RTL Design and Verification

SoC functionality is captured in RTL abstraction in Verilog and VHDL source code. The functionality is verified in simulation and FPGA prototyping. SoC Hub searches HW designers capable to contribute SoC IP development and integration activities such as RISC-V CPUs, deep-learning accelerators, video encoders, SoC platform peripherals, memory controllers, off-chip protocol stack IPs and Network-on-Chip interconnects. Needed competences are interest in modern SoC hardware development and skills on RTL development. The actual tasks will be adjusted according to the applicant’s competence and interests.

Position 2: Real-Time System Developer

Real-time systems are a significant sector of embedded computing that remains dominated by solutions built on commercial platforms. One of the aims of SoC Hub is to develop novel, state-of-the-art hard real-time systems using and extending open-source hardware (RISC-V) and software frameworks. This activity provides a broad scope of tasks to learn and contribute to, including RTL design and verification, FPGA prototyping, software use case development with Rust and ASIC synthesis. Additionally, the opportunity to contribute on associated publications is provided and encouraged.

Position 3: ASIC Physical design 

The focus of SoC Hub is on ASIC chips, and therefore ASIC physical design is one of the key skills needed. Physical design tasks include netlist synthesis, Design-For-Test (DFT), Static Timing Analysis (STA), Formal Verification (FV), Placement, Routing and Design Rule Checking (DRC). The work is done with state-of-the-art ASIC technology libraries and design automation tools, Cadence Genus and Cadence Innovus.

Position 4: IP-Xact, Kamel and Chisel code generators for hardware 

Modern SoC design involves design automation. This task involves development of RTL code generator with Python based framework, Chisel hardware construction language and/or IP-XACT descriptions. The outcome is a new IP-block or subsystem for the next SoC Hub chips. This task offer chance to adopt highly disruptive techniques. The specific language and IP-block will be specified based on the skills level. Good programming and digital design skills are required.

Position 5: GPGPU Hardware Platform Development

Modern scientific modeling and simulation problems and especially the AI models require huge amounts of compute power and memory throughput. The massively parallel nature of these applications is well suited for general-purpose graphics processing unit style of accelerators (GPGPUs). We are developing a hardware platform to be able to automatically customize and generate new GPGPUs and are looking for HW designers to help us implement the various components involved. Required basic skills include digital design with HDLs such as VHDL & Verilog and basic knowledge of computer architecture.

Position 6: Software design & development of electronic design automation tooling

Software development focused research assistant will contribute to ongoing improvements in our Electronic Design Automation (EDA) tools. The focus will be on rewriting and/or optimizing these tools for use in SoC design primarily using Rust, with additional proficiency in C++ and Qt considered beneficial. Responsibilities include collaborating with cross-disciplinary teams on the redesign and optimization of EDA tools, enhancing memory map editing features, and actively participating in the development of device tree generation for system representation for Linux and derivatives. The ideal candidate should possess proficiency in Rust programming with an understanding of C++ and Qt, and have previous familiarity with EDA tools. Preferred skills include familiarity with FPGA and ASIC design and knowledge of hardware description languages (Verilog, VHDL). The role emphasizes engagement in open-source development, encouraging contributions that benefit the broader EDA community.

How to apply

Read more and send your application here!

We are reading applications as they come in so if you are interested please send your application as soon as possible.

The closing date for applications is 18 February 2024.


For further information, please contact: