Join our growing SoC Hub team at Tampere University! We are now looking for several research assistants to work with us during the summer 2022.
The SoC Hub team handles all aspects of System-on-Chip design: specification, automation tools, RTL design, verification, SW architecture and tools, physical design and sample testing of chips fabricated in leading foundries. This includes handling of system topics like memory architectures, system throughput, use case base verification as well as dedicated module developments such as ML/AI, security, interconnect, RISC-V architectures as examples.
We are looking for enthusiastic, hard-working and motivated Research Assistants with BSc or MSc degree to work for SoC Hub. The interns will be supervised by our researchers and staff.
Job descriptions for the positions:
Position 1: FPGA prototyping
SoC Hub chips are verified both in simulations and synthesizing the designs on FPGA. This not only ensures functional correctness but also enables the SW development for the HW platform to start earlier. However, synthesizing a design on an FPGA differs from an ASIC in certain areas e.g. on-chip memories and clocking. The goal is to minimize platform specific configurations in the design flow. In addition, the physical SoC Hub chip samples are soldered onto a custom board that is connected to an FPGA board for testing. The goal with these is to create FPGA designs for sample testing which act as an intermediate for data between the SoC sample and external data inputs/outputs. We are searching for trainees or master thesis workers to contribute to both use cases. FPGA toolflow, RTL design and HW/SW co-design skills are preferred.
Position 2: RTL Design and Verification
SoC functionality is captured in RTL abstraction in Verilog and VHDL source code. The functionality is verified in test benches that have designs of their own. SoC Hub searches HW designers that can take signal processing and wireless communications algorithms and implement them in RTL, most preferably using High-Level Synthesis and IP-XACT. In addition, contributions to general purpose blocks like processor cores and network-on-chip designs would be welcome. Needed competences are interest in modern SoC hardware development and skills on RTL development. The actual tasks will be adjusted according to the applicant’s competence and interests.
Position 3: IP-Xact, Kamel and Chisel code generators for hardware
Modern SoC design involves design automation. This task involves development of RTL code generator with Python based framework, Chisel hardware construction language and/or IP-XACT descriptions. The outcome is a new IP-block or subsystem for the next SoC Hub chips. This task offer chance to adopt highly disruptive techniques. The specific language and IP-block will be specified based on the skills level. Good programming and digital design skills are required.
Position 4: Linux driver development for RISC-V based processor sub-system with custom peripherals including UART, I2C, SPI, SD card
The first SoC Hub chip “Ballast” is a large multi-processor chip with five processor and machine learning subsystems. All subsystems can access shared external and internal resources, which needs efficient arbitration and abstraction for the application SW development. In addition, the processor subsystems run Linux and RT operating systems. This task contributes to the development of partially automated firmware and drivers generation, as well as development of the tests and demonstrations on the versatile chip features. Embedded systems programming is preferred skills.
Position 5: High-speed SerDes design
SoC Hub offers opportunities to participating in research and design activities aimed at developing cutting-edge technology that will enable high-speed serial links for future high-performance computing/communication platforms with several tens of Gbps data rate over a single wire. Activities include behavioral modeling and characterization of the physical layer of the link, development of necessary hardware block including channel coding and other codecs (8b10b, 64b66b, scrambling, etc.), design of clock-data recovery (CDR) architecture, design of synchronization architecture, and link characterization hardware for SoCs. Skills of interest include, but are not limited to, communication system modeling with MATLAB, digital hardware design with HDLs like VHDL/Verilog, digital hardware design knowledge, digital design verification/validation with appropriate software (ModelSim, Synopsys, Cadence Innovus etc.). The actual tasks will be adjusted according to the applicant’s competence and interests.
Position 6: Analog/mixed-signal circuit design for high-speed serial links
SoC Hub offers opportunities to participating in research and design activities aimed at developing cutting-edge technology that will enable high-speed serial links for future high-performance computing/communication platforms with several tens of Gbps data rate over a single wire. Activities include design of high-performance analog/mixed-signal circuits for high-speed serial link frontend including LVDS driver/receiver, channel equalizer circuits, custom IO pads for the SoC, frequency and phase synchronization circuits, clock generation circuits etc. Skills of interest include, but are not limited to, circuit design and simulation with software like Cadence, behavioral modeling with Verilog-A, sign-off verification (DRC, LVS, parasitic extraction, PVT variation analysis), characterization of transmission lines etc. The actual tasks will be adjusted according to the applicant’s competence and interests.
Position 7: Application-specific Processor Co-Design Tooling
SoCs usually include multiple accelerator IPs with different degrees of flexibility. In this task, you will be involved with the OpenASIP project. OpenASIP is the open source application-specific instruction-set processor tool flow developed by TAU which is used to design software programmable co-processors of the SoC Hub chips for accelerating AI, audio and/or image signal processing tasks. The toolset has various aspects that will be improved, ranging from its retargetable compiler down to the efficient hardware generation capabilities.
How to apply
We are reading applications as they come in so if you are interested please send your application as soon as possible.
The closing date for applications is 11 March 2022.
For further information, please contact: