SoC Hub’s founding team consists of six professors. The projects conducted within the SoC Hub will eventually bring together dozens of professors and their research groups at Tampere University.
The System-on-Chip prototypes will be developed together in teams that include experts from the partner companies and the university’s research groups.
Dr. Ari Kulmala received his Ph.D. degree in 2009 from Tampere University of Technology (TUT). Currently he is working with System-on-Chip architectures and commercialization as a freelancer for Technology Innovation Institute (TII) of Abu Dhabi and also holds the position of Professor of Practice at Tampere University. His experience on System-on-Chip design ranges from small power mobile devices to large-scale processing infrastructure devices and data center applications. After working from 2003 to 2008 at Tampere University of Technology, in 2009, he joined Wireless Modem unit of Devices R&D at Nokia as a technical digital ASIC project manager. After Renesas Electronics acquired the unit he worked at Renesas Mobile from 2010 to 2013. In 2013, he joined Nokia Networks and headed several organizations, joined Tampere University in 2020, and headed the establishment of a Digital IC site for Nordic Semiconductor in 2021.
Timo Hämäläinen is a professor of Computer Engineering and the head of Computing Sciences at Tampere University. At SoC Hub he contributes to the ecosystem management, leads and supervises research projects and participates in SoC Hub ecosystem building. His personal research and teaching activities include System-on-Chip design methodologies and tools, as well as SoC architectures and systems. He is responsible of embedded systems study module for the digital design and computer engineering parts, which are the digital body of the SoC. Timo’s main current research interest is agile HW design methodologies including SW with the main idea of code generators at multiple levels of design abstraction. He is leading the System-on-Chip research group that develops Kactus2, the most well-known open source IP-XACT SoC tool, as well as architecture, IP-blocks and firmware for real chip prototypes. Timo was one of the first developers of DSP– and FPGA-based neural network computers in the first wave of machine learning and is excited to take AI computing to date in SoC Hub. The research group has optimized and implemented Machine Learning applications on mobile and embedded devices and develops ML acceleration blocks for the SoC Hub chips. Timo has also contributed to parallel video coding implementations, the latest one being fiber optics connected FPGA accelerated cloud.
Timo is the author of over 60 journal and 200 conference papers and has led over 30 research projects. He has also experience on technology transfer from research to companies and fundraising for research spin-offs.
Professor Mikko Valkama is the head of Electrical Engineering Unit at Tampere University, and he also leads the university’s radio systems and algorithms research. Mikko is expert in wireless communication, especially in novel transceiver algorithms. Within the framework of SoC Hub, he has specific expertise in physical layer processing algorithms in radio networks in general and particularly in 5G NR context. Mikko has been leading and supervising R&D work in radio systems and algorithms field since 2004, supervised 22 doctoral thesis works and co–authored close to 500 referee publications.
Professor Karri Palovuori is the digital ASIC backend and chip packaging specialist. He contributes to the chip testing process with designing printed circuit boards (PCB). Karri implemented his first full-custom neural network IC already in the first wave of Artificial Intelligence in the 90’s and he is a professional in all the essential phases of IC development span, from algorithm design to physical testing. He has been the main IC design professor since year 2000 and guided several physically realized IC design student projects. Currently Karri main focus is on full spectrum (innovation from bare metal to cloud) embedded systems implementations, which has an excellent synergy to the SoC Hub integration and application phases.
Pekka Jääskeläinen is a professor of Computer Engineering at the unit of Computing Sciences at Tampere University. He leads the university’s Customized Parallel Computing (CPC) research group. Pekka brings to SoC Hub his parallel computing and customized processor design expertise. He has nearly 20 years of experience in various aspects of high performance low power computing, ranging from customized processors up to low latency distributed computing implementations. In addition to his publication activities, he leads the development of the open source application-specific instruction-set processor toolset OpenASIP as well as the widely adapted OpenCL implementation platform Portable Computing Language (PoCL). Pekka’s current research interests include methods and tools to reduce the engineering effort involved in design and programming of diverse heterogeneous platforms (including CPUs, DSPs, GPUs, ASICs, FPGAs and accelerators), hardware and compiler techniques to reduce the energy consumption of instruction-set architectures, and low latency distributed implementations of computationally challenging algorithms such as photorealistic graphics rendering.
Jarno Vanne is a professor of Computer Engineering in the unit of Computing Sciences at Tampere University. Jarno is the expert in video coding and contributes to SoC hub with video IP and AI-enhanced video subsystems. He is the founder and leads the university‘s Ultra Video research group which is best known for the Kvazaar open source video encoder. The group is also able to deliver a bunch of other compute-intensive media processing applications to SoC Hub. The innovativeness lies in the semi-automatic design flow from software specification to CPU, FPGA and now also to ASICs in SoC Hub.
Jarno received his M.Sc. degree in information technology in 2002 and his Ph.D. degree in computing and electrical engineering in 2011 from the Tampere University of Technology. His research activities include high efficiency and versatile video coding (HEVC/VVC), immersive 3D/360 video coding for virtual/augmented/mixed/extended reality (VR/AR/MR/XR), deep learning based video coding/annotation, and related technology deployment in next-generation media applications. Jarno has been the project manager for 17 international and national research projects and the author of 70 peer-reviewed scientific publications.