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Revolutionizing Chip Design Process Through Designer Productivity

…locations and wires at this point is done by engineer manually. Circuits grew as the demand for more complexity to be integrated grew. There was demand for documenting the circuit… […]

First System-on-Chip developed in a pioneering project between Tampere University and companies

…systems. One of the key goals of the SoC Hub project is to enable rapid prototyping for new ideas, for example, in IoT, machine learning or 5G and 6G technologies… […]

What is an ASIC and how to build one?

… Source: https://www.anandtech.com/show/9330/exynos-7420-deep-dive/2 Due to importance of high-bandwidth interconnect and previous research and development by our group, we selected a NoC as… […]

SoC Hub takes part in the development of European RISC-V ecosystem in TRISTAN project

…include cores and peripherals for the complete SoC architectures and accompanying software. The goals are very similar to the SoC Hub project funded by Business Finland, and it brings the… […]

The second System-on-Chip developed by SoC Hub has been taped out

…with the Tackle chip was on developing completely new SoC platform and connectivity IPs. The programmable DMA controller, LP-DDR2 memory controller, and High Speed Serdes datalink were designed, verified and… […]

Workshop: Embedded Linux on a RISC-V processor

…both emulators and actual hardware for development. No prior experience with embedded development is required, general interest and basic Linux experience is sufficient. The hands-on training is limited to 50… […]

Siemens EDA webinar on 20 June: Managing the Complexity of an HEVC Encoder (Kvazaar) Implementation on FPGA with Catapult HLS

…in Finland, Ultra Video Group. His current research interests include High-Level Synthesis, video encoding, hardware and system-on-a-chip designing, FPGAs, and Linux kernel driver development. About the webinar: HEVC (H.265) is… […]

Presentations at HiPEAC’s Computing Systems Week

…the perceived benefits in the short-term. In their recent research work, the research group took an open-source implementation of a RISC-V microprocessor as is and packaged it with Kactus2. Here… […]

Webinar: Introduction to Cadence Design Systems digital backend flow

…using Cadence tools for design of its SoCs. Register for the webinar by 15.6.2021 here Registration is free. The number of participants is limited to 50 participants. Agenda Times… […]

Improving Instruction Stream Energy-Efficiency with Code Compression

…Finland, Spain, Italy. Written by Joonas Multanen and Pekka Jääskeläinen 1 Andrae, Anders S.G. Total Consumer Power Consumption Forecast, 2017,https://www.researchgate.net/publication/320225452_Total_Consumer_Power_Consumption_Forecast 2 Joonas Multanen, Kari Hepola, Pekka Jääskeläinen: “Programmable Dictionary… […]