…consortium project funded by Business Finland. The partners include Tampere University, Nokia, CoreHW, VLSI Solution, Siru Innovations, TTTEch Flexibilis, Procemex, Wapice and Cargotec. SoC Hub will develop three chips by… […]
…the team started to wake up the chip right away. Wake-up, which is the first testing task, shows whether the design of the chip has been successful. – The testing… […]
…experience in the field are appreciated. The recommended skills include, for example, some of the following: HDL tools (VHDL, Verilog, SystemVerilog) High-Level Synthesis and SystemC based tools (C++) Repositories (Git),… […]
…2024 from 17.00 to 20.30. Register here Program (tentative): – 16:15 doors open – 17:00 program starts – 20:30 program ends Speakers: Cut Creator the scratch Egui thingy, Prof. Per… […]
…is to keep the pace of developing one chip per year. ___ SoC Hub is funded by European Regional Development Fund and Business Finland… […]
…member of our course catalog. Starting from the spring 2022, we will build on these experiences and continue training new verification engineers on a new course COMP.CE.420 System-on-Chip Verification. Verification… […]
…link, development of necessary hardware block including channel coding and other codecs (8b10b, 64b66b, scrambling, etc.), design of clock-data recovery (CDR) architecture, design of synchronization architecture, and link characterization hardware… […]
…ASIC chips, the ASIC physical design is one of the key skills needed. Physical design tasks include netlist synthesis, Design-For-Test (DFT), Static Timing Analysis (STA), Formal Verification (FV), Placement, Routing… […]
…website. Photo: The chip packaging design (on left) and final assembly (on right) of the SoC Hub chip ”Ballast”. ___ SoC Hub is funded by… […]
…a wide variety of technologies with latest ones, such as 3nm, being targeted to high performance computing. However, in the Internet-of-Things domain, having expected yearly growth of more than 20%,… […]
Ecosystem initiative for a world-class co-developed Finnish System-on-Chip
