Accelerating Imaging Algorithms with Catapult High-Level Synthesis
10 & 11 November 2021, 15.30–19.30 (UTC +2)
SoC Hub online workshop hosted by Siemens
This online workshop shows how Catapult High-Level Synthesis can be used to rapidly take a floating-point image processing algorithm written in C++ to a high-quality RTL implementation. In some cases, this algorithm can originate as code running on the embedded processor. The workshop provides an overview of why HLS is being adopted today, covers the basics of HLS, and provides a step-by-step approach, including hands-on labs. A floating-point edge detection algorithm will be used as an example. Part of the algorithm will be migrated from software running on an embedded processor into a high-performance RTL implementation.
Register for the workshop by 7 November 2021 here
This workshop is targeted at:
* Algorithm and hardware engineers who want to learn more about HLS and where they fit within the HLS design flow
* Embedded software developers considering migration of algorithms into hardware to improve performance and efficiency
* Management team members looking to understand the productivity benefits of HLS.
This workshop is scheduled to be a combination of lecture and lab. There is a limit of 20 participants for the lab section.
Due to coordinating timezones with the PST we will split the workshop into two days with 4 hours each day. Approximately 2 hours lecture/2 hours lab.
Agenda
Day 1
Introduction to High-Level Synthesis (30 minutes)
Overview of HLS Benefits
Architecting for HLS – who’s involved in the design process
HLS 101
Edge Detect Algorithm (30 minutes)
Overview of the floating-point implementation
Profile, identify candidates for acceleration
Algorithmic C++ bit-accurate data types
Modeling streaming interfaces in untimed C++. ‘
Lab1 – Compiling, executing, and profiling edge detector (30 minutes)
Partitioning (60 minutes)
Partitioning the edge detect algorithm for synthesis
Making the C++ synthesizable
Catapult design, analysis, and automated verification flow
Lab2 – Initial synthesis and analysis of performance bottlenecks using Catapult HLS (45 Minutes)
Day 2
System Integration (45 minutes)
Integrating with an embedded processor
Software interfaces
System level simulation and profiling
Lab3 – Executing and profiling in a processor design (45 minutes)
Architecting for performance and efficiency (60 Minutes)
Optimizing the memory architecture
Going from dual-port to single-port memory
Implementing a circular buffer architecture
Catapult automated power analysis and optimization
Lab4 – Synthesis and analysis of the optimized memory architecture (60 minutes)
Wrap-up (15 minutes)
Your Instructors
Mike Fingeroff
HLS Technologist for the Catapult HLS Platform at Siemens EDA (formally Mentor Graphics) since 2002. His areas of interest include Machine Learning, DSP, and high-performance video hardware. Prior to working for Siemens, he worked as a hardware design engineer developing real-time broadband video systems. Mike is the author of the premier textbook for using HLS for design “The High-Level Synthesis (HLS) Blue Book”.
Russell Klein
HLS technologist for the Catapult HLS Platform at Siemens EDA (formally Mentor Graphics). He has published a number of papers on system design and optimization through hardware/software repartitioning. He holds several of patents for EDA tools in the area of SoC design and verification. Mr. Klein has over 25 years of experience developing design and debug solutions which span the boundary between hardware and software.
